The present invention relates to a semiconductor device and a method for manufacturing it, and specifically relates to a semiconductor device including MIS (Metal Insulator Semiconductor) transistors different in structure for coping with a plurality of source voltages and a method for manufacturing it.
As is known, the gate length of MIS transistors used in large scale integrated circuits has been reduced to less than 0.1 μm, and further development for miniaturization is being advanced. In general, a plurality of source voltages are supplied to a semiconductor chip, wherein the semiconductor chip is composed of a core transistor that is driven at a low source voltage for processing and an I/O transistor that is driven at a high source voltage for transmitting data to and from another chip or for dealing with analog data. The core transistor dominantly occupies the chip area, and the processing speed of the chip depends on the performance of the core transistor. Therefore, the size and the performance of the core transistor gather attention in many cases (as for the foregoing, see Japanese Patent Application Laid Open Publication Nos. 6-204472A, 2002-118255A, 2004-39694A, and 2004-533728A, for example).
The core transistor has been miniaturized progressively along the scaling law while miniaturization of only a contact diameter or a distance between a contact and a gate has been promoted in the I/O transistor. Under the circumstances, the dimensional difference between the core transistor and the I/O transistor grows wider and wider in recent years.
FIG. 6 shows the relationship between the semiconductor process generation (the axis of abscissas) and the circuit areas (arbitrary unit) of the core transistor and the I/O transistor (the axis of ordinates on the left) and the relationship between the semiconductor process generation (the axis of abscissas) and the circuit occupancy (%) of the I/O transistor (the axis of ordinates on the right).
As can be cleared from FIG. 6, the circuit area of the I/O transistor in a chip is no more than 10% in 0.18 μm generation. In association with remarkable reduction in circuit area of the core transistor, the circuit occupancy of the I/O transistor increases to 30% or more in some chips in 65 nm generation. If such rate reduction in circuit area of the core transistor occupying a chip would progress, there would be little or no difference in circuit area in a chip between the I/O transistor and the core transistor in 45 nm generation. This leads to slowing down of miniaturization of a chip as a whole, resulting in less scaling effect attained.